Integrated circuit processing technology has been developed which allows for the formation of bipolar and MOS circuits on the same die (or chips). Bipolar and MOS circuits have different characteristics which can be used to complement each other. Bipolar circuits tend to be faster than MOS circuits whereas MOS circuits tend to consume less power than bipolar circuits. The low power of MOS allows for, among other things, more transistors on a chip. This is particularly advantageous in memories. Bipolar and MOS circuits have been combined on the same chip in static random access memories (SRAMs) for example.
In such a memory the bipolar circuits are used primarily in the peripheral circuitry for speed. Some of the peripheral circuits are CMOS. The memory array itself is MOS circuitry for density. The signals generated externally are received by bipolar circuitry and then internally provided to CMOS circuits. There must then be provided internally a circuit for making the transition from bipolar level signals to CMOS level signals.
In the case where emitter coupled logic (ECL) circuits are used as the bipolar circuits, there is a particular problem with level translation because ECL logic states vary only about one volt whereas CMOS logic states swing the full rail of the power supply voltage. The typical power supply voltage is about 5 volts. That the difference between a logic high and a logic low is only one volt in ECL is part of the reason that ECL circuits are so fast. On the other hand a part of the reason that CMOS is low power is because the logic levels swing the entire power supply voltage. One of the requirements then of an integrated circuit which combines the advantages of CMOS and ECL is that there be an ECL to CMOS translator which does not cause excessive delay. In the past this translation has been accomplished by having a P channel device receive the ECL signal. This has created problems because the P channel device must be made very large because the one volt logic state differential of ECL does not cause a very large gate to source voltage differential on the P channel transistor. The ECL transistors do not track the P channel transistors over process variations so there is also a problem in guaranteeing that the P channel transistor is non-conductive for the logic high output of the ECL circuit.